Computer System Architecture

321. Which are designed to interpret a specified number of instruction code:

1. Programmer
2. Processors
3. Instruction
4. Opcode

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322. Which code is a string of binary digits:

1. Op code
2. Instruction code
3. Parity code
4. Operand code

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323. The list of specific instruction supported by the CPU is termed as its ____________:

1. Instruction code
2. Parity set
3. Instruction set
4. None of these

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324. ____________ is divided into a number of fields and is represented as a sequence of bits:

1. instruction
2. instruction set
3. instruction code
4. parity code

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325. Which unit is necessary for the execution of instruction:

1. Timing
2. Control
3. Both
4. None of these

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326. Which unit provide status , timing and control signal:

1. Timing and control unit
2. Memory unit
3. Chace unit
4. None of these

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327. Which unit acts as the brain of the computer which control other peripherals and interfaces:

1. Memory unit
2. Cache unit
3. Timing and control unit
4. None of these

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328. It contains the ____________ stack for PC storage during subroutine calls and input/output interrupt services:

1. Seven- level hardware
2. Eight- level hardware
3. One- level hardware
4. Three- level hardware

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329. Which unit works as an interface between the processor and all the memories on chip or off- chip:

1. Timing unit
2. Control unit
3. Memory control unit
4. All of these

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330. The maximum clock frequency is ____________:

1. 45 MHZ
2. 50 MHZ
3. 52 MHZ
4. 68 MHZ

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